dor_id: 45478

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856.4.0.u: https://jart.icat.unam.mx/index.php/jart/article/view/71/70

100.1.#.a: Pedroza de la Crúz, Adrián; Reyes Barón, José Roberto; Ortega Cisneros, Susana; Raygoza Panduro, Juan José; Carrazco Díaz, Miguel Ángel; Loo Yau, José Raúl

524.#.#.a: Pedroza de la Crúz, Adrián, et al. (2015). Characterization and synthesis of a 32-bit asynchronous microprocessorin synchronous reconfigurable devices. Journal of Applied Research and Technology; Vol. 13 Núm. 5. Recuperado de https://repositorio.unam.mx/contenidos/45478

245.1.0.a: Characterization and synthesis of a 32-bit asynchronous microprocessorin synchronous reconfigurable devices

502.#.#.c: Universidad Nacional Autónoma de México

561.1.#.a: Instituto de Ciencias Aplicadas y Tecnología, UNAM

264.#.0.c: 2015

264.#.1.c: 2015-10-01

653.#.#.a: Asynchronous; Microprocessor; Floating point; FPGA delay macro; Real time1

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001.#.#.#: 074.oai:ojs2.localhost:article/71

041.#.7.h: eng

520.3.#.a: This paper presents the design, implementation, and experimental results of 32-bit asynchronous microprocessor developed in a synchronousreconfigurable device (FPGA), taking advantage of a hard macro. It has support for floating point operations, such as addition, subtraction,and multiplication, and is based on the IEEE 754-2008 standard with 32-bit simple precision. This work describes the different blocks of themicroprocessors as delay modules, needed to implement a Self-Timed (ST) protocol in a synchronous system, and the operational analysis of theasynchronous central unit, according to the developed occupations and speeds. The ST control is based on a micropipeline used as a centralizedgenerator of activation signals that permit the performance of the operations in the microprocessor without the need of a global clock. This workcompares the asynchronous microprocessor with a synchronous version. The parameters evaluated are power consumption, area, and speed. Bothcircuits were designed and implemented in an FPGA Virtex 5. The performance obtained was 4 MIPS for the asynchronous microprocessor against1.6 MIPS for the synchronous.All Rights Reserved © 2015 Universidad Nacional Autónoma de México, Centro de Ciencias Aplicadas y Desarrollo Tecnológico. This is anopen access item distributed under the Creative Commons CC License BY-NC-ND 4.0.

773.1.#.t: Journal of Applied Research and Technology; Vol. 13 Núm. 5

773.1.#.o: https://jart.icat.unam.mx/index.php/jart

022.#.#.a: ISSN electrónico: 2448-6736; ISSN: 1665-6423

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doi: https://doi.org/10.1016/j.jart.2015.10.004

harvesting_date: 2023-11-08 13:10:00.0

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last_modified: 2024-03-19 14:00:00

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Artículo

Characterization and synthesis of a 32-bit asynchronous microprocessorin synchronous reconfigurable devices

Pedroza de la Crúz, Adrián; Reyes Barón, José Roberto; Ortega Cisneros, Susana; Raygoza Panduro, Juan José; Carrazco Díaz, Miguel Ángel; Loo Yau, José Raúl

Instituto de Ciencias Aplicadas y Tecnología, UNAM, publicado en Journal of Applied Research and Technology, y cosechado de Revistas UNAM

Licencia de uso

Procedencia del contenido

Cita

Pedroza de la Crúz, Adrián, et al. (2015). Characterization and synthesis of a 32-bit asynchronous microprocessorin synchronous reconfigurable devices. Journal of Applied Research and Technology; Vol. 13 Núm. 5. Recuperado de https://repositorio.unam.mx/contenidos/45478

Descripción del recurso

Autor(es)
Pedroza de la Crúz, Adrián; Reyes Barón, José Roberto; Ortega Cisneros, Susana; Raygoza Panduro, Juan José; Carrazco Díaz, Miguel Ángel; Loo Yau, José Raúl
Tipo
Artículo de Investigación
Área del conocimiento
Ingenierías
Título
Characterization and synthesis of a 32-bit asynchronous microprocessorin synchronous reconfigurable devices
Fecha
2015-10-01
Resumen
This paper presents the design, implementation, and experimental results of 32-bit asynchronous microprocessor developed in a synchronousreconfigurable device (FPGA), taking advantage of a hard macro. It has support for floating point operations, such as addition, subtraction,and multiplication, and is based on the IEEE 754-2008 standard with 32-bit simple precision. This work describes the different blocks of themicroprocessors as delay modules, needed to implement a Self-Timed (ST) protocol in a synchronous system, and the operational analysis of theasynchronous central unit, according to the developed occupations and speeds. The ST control is based on a micropipeline used as a centralizedgenerator of activation signals that permit the performance of the operations in the microprocessor without the need of a global clock. This workcompares the asynchronous microprocessor with a synchronous version. The parameters evaluated are power consumption, area, and speed. Bothcircuits were designed and implemented in an FPGA Virtex 5. The performance obtained was 4 MIPS for the asynchronous microprocessor against1.6 MIPS for the synchronous.All Rights Reserved © 2015 Universidad Nacional Autónoma de México, Centro de Ciencias Aplicadas y Desarrollo Tecnológico. This is anopen access item distributed under the Creative Commons CC License BY-NC-ND 4.0.
Tema
Asynchronous; Microprocessor; Floating point; FPGA delay macro; Real time1
Idioma
eng
ISSN
ISSN electrónico: 2448-6736; ISSN: 1665-6423

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