dor_id: 45658

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351.#.#.b: Journal of Applied Research and Technology

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856.4.0.u: https://jart.icat.unam.mx/index.php/jart/article/view/269/266

100.1.#.a: M. Sait, Sadiq; T. Sheikh, Ahmad; H. El Maleh, Aiman

524.#.#.a: M. Sait, Sadiq, et al. (2013). Cell Assignment in Hybrid CMOS/Nanodevices Architecture Using a PSO/SA Hybrid Algorithm. Journal of Applied Research and Technology; Vol. 11 Núm. 5. Recuperado de https://repositorio.unam.mx/contenidos/45658

245.1.0.a: Cell Assignment in Hybrid CMOS/Nanodevices Architecture Using a PSO/SA Hybrid Algorithm

502.#.#.c: Universidad Nacional Autónoma de México

561.1.#.a: Instituto de Ciencias Aplicadas y Tecnología, UNAM

264.#.0.c: 2013

264.#.1.c: 2013-10-01

653.#.#.a: CMOL; combinatorial optimization; search heuristics; nanofabric; assignment; VLSI; hybrid heuristics

506.1.#.a: La titularidad de los derechos patrimoniales de esta obra pertenece a las instituciones editoras. Su uso se rige por una licencia Creative Commons BY-NC-SA 4.0 Internacional, https://creativecommons.org/licenses/by-nc-sa/4.0/legalcode.es, para un uso diferente consultar al responsable jurídico del repositorio por medio del correo electrónico gabriel.ascanio@icat.unam.mx

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041.#.7.h: spa

520.3.#.a: In recent years, substantial advancements have been made in VLSI technology. With the introduction of CMOL(Cmos\nanowire\MOLecular Hybrid), higher circuit densities are possible. In CMOL there is an additional layer of nanofabricon top of CMOS stack. Nanodevices that lie between overlapping nanowires are programmable and can implement anycombinational logic using a netlist of NOR gates. The limitation on the length of nanowires put a constraint on theconnectivity domain of a circuit. The gates connected to each other must be within a connectivity radius; otherwise an extrabuffer is inserted to connect them. Particle swarm optimization (PSO) has been used in a variety of problems that are NPhard.PSO compared to the other iterative heuristic techniques is simpler to implement. Besides, it delivers comparableresults. In this paper, a hybrid of PSO and simulated annealing (SA) for solving the cell assignment in CMOL, an NP-hardproblem, is proposed. The proposed method takes advantage of the exploration and exploitation factors of PSO and theintrinsic hill climbing feature of SA to reduce the number of buffers to be inserted. Experiments conducted on ISCAS’89benchmark circuits and a comparison with other heuristic techniques, are presented. Results showed that the proposedhybrid algorithm achieved better solution in terms of buffer count in reasonable time.

773.1.#.t: Journal of Applied Research and Technology; Vol. 11 Núm. 5

773.1.#.o: https://jart.icat.unam.mx/index.php/jart

022.#.#.a: ISSN electrónico: 2448-6736; ISSN: 1665-6423

310.#.#.a: Bimestral

264.#.1.b: Instituto de Ciencias Aplicadas y Tecnología, UNAM

doi: https://doi.org/10.1016/S1665-6423(13)71573-6

harvesting_date: 2023-11-08 13:10:00.0

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last_modified: 2024-03-19 14:00:00

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Artículo

Cell Assignment in Hybrid CMOS/Nanodevices Architecture Using a PSO/SA Hybrid Algorithm

M. Sait, Sadiq; T. Sheikh, Ahmad; H. El Maleh, Aiman

Instituto de Ciencias Aplicadas y Tecnología, UNAM, publicado en Journal of Applied Research and Technology, y cosechado de Revistas UNAM

Licencia de uso

Procedencia del contenido

Cita

M. Sait, Sadiq, et al. (2013). Cell Assignment in Hybrid CMOS/Nanodevices Architecture Using a PSO/SA Hybrid Algorithm. Journal of Applied Research and Technology; Vol. 11 Núm. 5. Recuperado de https://repositorio.unam.mx/contenidos/45658

Descripción del recurso

Autor(es)
M. Sait, Sadiq; T. Sheikh, Ahmad; H. El Maleh, Aiman
Tipo
Artículo de Investigación
Área del conocimiento
Ingenierías
Título
Cell Assignment in Hybrid CMOS/Nanodevices Architecture Using a PSO/SA Hybrid Algorithm
Fecha
2013-10-01
Resumen
In recent years, substantial advancements have been made in VLSI technology. With the introduction of CMOL(Cmos\nanowire\MOLecular Hybrid), higher circuit densities are possible. In CMOL there is an additional layer of nanofabricon top of CMOS stack. Nanodevices that lie between overlapping nanowires are programmable and can implement anycombinational logic using a netlist of NOR gates. The limitation on the length of nanowires put a constraint on theconnectivity domain of a circuit. The gates connected to each other must be within a connectivity radius; otherwise an extrabuffer is inserted to connect them. Particle swarm optimization (PSO) has been used in a variety of problems that are NPhard.PSO compared to the other iterative heuristic techniques is simpler to implement. Besides, it delivers comparableresults. In this paper, a hybrid of PSO and simulated annealing (SA) for solving the cell assignment in CMOL, an NP-hardproblem, is proposed. The proposed method takes advantage of the exploration and exploitation factors of PSO and theintrinsic hill climbing feature of SA to reduce the number of buffers to be inserted. Experiments conducted on ISCAS’89benchmark circuits and a comparison with other heuristic techniques, are presented. Results showed that the proposedhybrid algorithm achieved better solution in terms of buffer count in reasonable time.
Tema
CMOL; combinatorial optimization; search heuristics; nanofabric; assignment; VLSI; hybrid heuristics
Idioma
spa
ISSN
ISSN electrónico: 2448-6736; ISSN: 1665-6423

Enlaces