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351.#.#.b: Journal of Applied Research and Technology

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856.4.0.u: https://jart.icat.unam.mx/index.php/jart/article/view/550/546

100.1.#.a: Garda, E.; Guzmán, M.; Torres, D.

524.#.#.a: Garda, E., et al. (2005). A HARDWARE IMPLEMENTATION OF PUNGURED CONVOLUTIONAL CODES TO COMPLETE A VITERBI DECODER CORE. Journal of Applied Research and Technology; Vol. 3 Núm. 02. Recuperado de https://repositorio.unam.mx/contenidos/45480

245.1.0.a: A HARDWARE IMPLEMENTATION OF PUNGURED CONVOLUTIONAL CODES TO COMPLETE A VITERBI DECODER CORE

502.#.#.c: Universidad Nacional Autónoma de México

561.1.#.a: Instituto de Ciencias Aplicadas y Tecnología, UNAM

264.#.0.c: 2005

264.#.1.c: 2005-08-01

653.#.#.a: Convolutional Coding; Vlterbi Decoding; Pundured Codes

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041.#.7.h: eng

520.3.#.a: This paper presents a VLSI (Very Large Scale Integration) implementation of high punctured convolutional codes.We present a new circuit architecture that is capable of processing up to 10 convolutional codes rate (n-1)/n withthe constraint length-7 derived by the puncturing technique from the basic rate-1/2. The present circuit wasdesigned in order to complete an existing Viterbi decoder core, adding some extra functionality such as aconvolutional encoder, differential encoder/decoder, punctured convolutional encoder and symbol insertion todepuncture the received data. This extra functionality includes 10 different programmable coding rates without theneed to add additional logic in the system implementation, while other existing coders need it to attain highercoding rates. Therefore, a single chip solution is presented. The design was implemented in VHDL (Very High SpeedIntegrated Circuit Hardware Description Language) synthesized in Synopsys tool, and tested in a FPGA. Functionalverification was done, by means of simulation, to ensure that the circuit implements intended functionality. Suchsimulations were executed using Synopsys and a Sun Ultra Sparc 10 workstation. Different bit error probabilityperformance curves show an agreement between simulated and theoretical values.

773.1.#.t: Journal of Applied Research and Technology; Vol. 3 Núm. 02

773.1.#.o: https://jart.icat.unam.mx/index.php/jart

022.#.#.a: ISSN electrónico: 2448-6736; ISSN: 1665-6423

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doi: https://doi.org/10.22201/icat.16656423.2005.3.02.550

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Artículo

A HARDWARE IMPLEMENTATION OF PUNGURED CONVOLUTIONAL CODES TO COMPLETE A VITERBI DECODER CORE

Garda, E.; Guzmán, M.; Torres, D.

Instituto de Ciencias Aplicadas y Tecnología, UNAM, publicado en Journal of Applied Research and Technology, y cosechado de Revistas UNAM

Licencia de uso

Procedencia del contenido

Cita

Garda, E., et al. (2005). A HARDWARE IMPLEMENTATION OF PUNGURED CONVOLUTIONAL CODES TO COMPLETE A VITERBI DECODER CORE. Journal of Applied Research and Technology; Vol. 3 Núm. 02. Recuperado de https://repositorio.unam.mx/contenidos/45480

Descripción del recurso

Autor(es)
Garda, E.; Guzmán, M.; Torres, D.
Tipo
Artículo de Investigación
Área del conocimiento
Ingenierías
Título
A HARDWARE IMPLEMENTATION OF PUNGURED CONVOLUTIONAL CODES TO COMPLETE A VITERBI DECODER CORE
Fecha
2005-08-01
Resumen
This paper presents a VLSI (Very Large Scale Integration) implementation of high punctured convolutional codes.We present a new circuit architecture that is capable of processing up to 10 convolutional codes rate (n-1)/n withthe constraint length-7 derived by the puncturing technique from the basic rate-1/2. The present circuit wasdesigned in order to complete an existing Viterbi decoder core, adding some extra functionality such as aconvolutional encoder, differential encoder/decoder, punctured convolutional encoder and symbol insertion todepuncture the received data. This extra functionality includes 10 different programmable coding rates without theneed to add additional logic in the system implementation, while other existing coders need it to attain highercoding rates. Therefore, a single chip solution is presented. The design was implemented in VHDL (Very High SpeedIntegrated Circuit Hardware Description Language) synthesized in Synopsys tool, and tested in a FPGA. Functionalverification was done, by means of simulation, to ensure that the circuit implements intended functionality. Suchsimulations were executed using Synopsys and a Sun Ultra Sparc 10 workstation. Different bit error probabilityperformance curves show an agreement between simulated and theoretical values.
Tema
Convolutional Coding; Vlterbi Decoding; Pundured Codes
Idioma
eng
ISSN
ISSN electrónico: 2448-6736; ISSN: 1665-6423

Enlaces